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W25P240A 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W25P240A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports PentiumTM burst mode.
FEATURES
* Synchronous operation * Support 66/75 MHz bus speed * Single +3.3V power supply * Individual byte write capability * 3.3V LVTTL compatible I/O * Clock-controlled and registered input * Asynchronous output enable * Internal burst counter supports Intel burst mode * Packaged in 100-pin QFP
BLOCK DIAGRAM
A(15:0)
INPUT REGISTER 64K X 64 CORE ARRAY
CLK CE GW BWE BW(8:1) OE ADSC ADSP ADV
CONTROL LOGIC DATA I/O REGISTER
I/O(64:1)
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Publication Release Date: February 1998 Revision A4
W25P240A
PIN CONFIGURATION
I / O 3 4
I / O 3 3
/ B W 8
/ B W 7
/ B W 6
/ B W 5
// AA/ / B/ / / C DDA G OC L S S D W EWEE K P CV
/ B W 4
/ B W 3
/ B W 2
/ B W 1
I / O 3 2
I / O 3 1
I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 VDD VSS I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62
19999999999888888888 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 80 79 20 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 11 70 12 69 68 13 14 67 66 15 65 16 17 64 63 18 62 19 61 20 60 21 59 22 58 23 24 57 56 25 55 26 54 27 28 53 52 29 30 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 51 12345678901234567890
100-pin
QFP MO-108
I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 VSS VDD I/O 16 I/O 15 I/O 14 I/O 13 I/O 12 I/O 11 I/O 10 I/O 09 I/O 08 I/O 07 I/O 06 I/O 05 I/O 04 I/O 03
I / O 6 3
I AAAAAAAAA AAAAAAAI I / 7654321089111111/ / 012345OO O 6 12 4
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W25P240A
PIN DESCRIPTION
SYMBOL A0-A15 I/O1-I/O64 CLK TYPE Input, Synchronous I/O, Synchronous Input, Clock Input, Synchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Synchronous Input, Synchronous Input, Synchronous Host Address Data Inputs/Outputs Processor Host Bus Clock Chip Enables Global Write Byte Write Enable from Cache Controller Host Bus Byte Enables used with BWE Output Enable Input Internal Burst Address Counter Advance Address Status from chip set Address Status from CPU Power Supply Ground DESCRIPTION
CE
GW
BWE
BW1 - BW8
OE ADV ADSC
ADSP
VDD VSS
FUNCTIONAL DESCRIPTION
The W25P240A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports only one burst address sequence for IntelTM systems. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low.
Burst Address Sequence
A[1:0] External Start Address Second Address Third Address Fourth Address 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00
The device supports several types of write mode operations. BWE and BW [8:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor.
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Publication Release Date: February 1998 Revision A4
W25P240A
TRUTH TABLE
CYCLE Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set up the SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold are met. timings ADDRESS USED No External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current CE 1 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 ADSP X 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X ADSC 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 OE X X X 1 0 1 0 1 0 1 0 X X X X X X X DATA Hi-Z Hi-Z Hi-Z Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z WRITE* X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write
WRITE TABLE
READ/WRITE FUNCTION Read Read Write byte 1 I/O1-I/O8 Write byte 2 I/O9-I/O16 Write byte 2, byte 1
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
1 1 1 1 1
1 0 0 0 0
X 1 1 1 1
X 1 1 1 1
X 1 1 1 1
X 1 1 1 1
X 1 1 1 1
X 1 1 1 1
X 1 1 0 0
X 1 0 1 0
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W25P240A
Write Table, continued
READ/WRITE FUNCTION Write byte 3 I/O17-I/O24 Write byte 3, byte 1 Write byte 3, byte 2 Write byte 3, byte 2, byte 1 Write byte 4, I/O25-I/O32 Write byte 4, byte 1 Write byte 4, byte 2 Write byte 4, byte 2, byte 1 Write byte 4, byte 3 Write byte 4, byte 3, byte 1 Write byte 4, byte 3, byte 2 Write byte 4, byte 3, byte 2, byte 1 Write byte 5, I/O33-I/O40 Write byte 5, byte 1 Write byte 5, byte 2 Write byte 5, byte 2, byte 1 Write byte 5, byte 3 Write byte 5, byte 3, byte 1 Write byte 5, byte 3, byte 2 Write byte 5, byte 3, byte 2, byte 1 Write byte 5, byte 4 Write byte 5, byte 4, byte 1 Write byte 5, byte 4, byte 2 Write byte 5, byte 4, byte 2, byte 1 Write byte 5, byte 4, byte 3 Write byte 5, byte 4, byte 3, byte1 Write byte 5, byte 4, byte 3, byte2 Write byte 5, byte 4, byte 3, byte 2, byte 1 Write byte 6 Write byte 6, byte1 Write byte 6, byte2 Write byte 6, byte2, byte1 ..... and so on ..... Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 2, byte 1
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 ... 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ... 0
1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 ... 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ... 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... 0
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Publication Release Date: February 1998 Revision A4
W25P240A
Write Table, continued
READ/WRITE FUNCTION Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 1 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 2 Write all bytes Write all bytes
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
1 1 1 1 0
0 0 0 0 x
0 0 0 0 x
0 0 0 0 x
0 0 0 0 x
0 0 0 0 x
0 0 0 0 x
0 0 0 0 x
1 1 0 0 x
1 0 1 0 x
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to Vss Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to 4.6 VSS -0.5 to VDD +0.5 1.5 -65 to 150 0 to +55 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 3.15V to 3.6V, VSS = 0V, TA = 0 to 55 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current Standby Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, and data I/O pins in high-Z state defined in truth table IOL = +8.0 mA IOH = -4.0 mA TCYC min., I/O = 0 mA Unselected mode defined in truth table, VIN, VIO = VIH (min.) /VIL (max.) TCYC min.
MIN. -0.5 +2.0 -10 -10
TYP . -
MAX. +0.8 VDD +0.3 +10 + 10
UNIT V V A A
VOL VOH IDD ISB
2.4 -
-
0.4 350 80
V V mA mA
Note: Typical characteristics are measured at VDD = 3.3V, TA = 25 C.
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W25P240A
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 2 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS
AC Test Loads and Waveform
RL = 50 ohm VL = 1.5V OUTPUT Zo = 50 ohm 30 pF Including Jig and Scope
R1 320 ohm 3.3V OUTPUT 5 pF Including Jig and Scope (For TKHZ, TKLZ, TOHZ, TOLZ, R2 350 ohm
measurement)
3.0V 0V 2 nS
90% 10% 10%
90%
2 nS
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Publication Release Date: February 1998 Revision A4
W25P240A
AC Timing Characteristics
(VDD = 3.15V to 3.6V, VSS = 0V, TA = 0 to 55 C)
PARAMETER Add. Setup Time Add. Hold Time Write Data Setup Time Write Data Hold Time
ADV Setup Time ADV Hold Time ADSP Setup Time ADSP Hold Time ADSC Setup Time ADSC Hold Time
SYMBOL
TAS TAH TDS TDH TADVS TADVH TADSS TADSH TADCS TADCH TCES TCEH TWS TWH TCYC TKH TKL TKQ TKHZ TKLZ TKX TOE TOHZ TOLZ TOX
W25P240A-6 MIN. 1.5 1.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.0 1.0 13.3 5 5 2 0 2 0 0 MAX. 6 13.3 6 6 -
W25P240A-6A MIN. 1.5 1.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.0 1.0 15 6 6 2 0 2 0 0 MAX. 7 15 7 7 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
NOTE
CE , Setup Time CE , Hold Time
GW , BWE X Setup Time GW , BWE X Hold Time
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock to Output Valid Clock to Output High-Z Clock to Output Low-Z Clock to Output Invalid Output Enable to Output Valid Output Enable to Output High-Z Output Enable to Output Low-Z Output Enable to Output Invalid
Note Note Note
Note Note
Note: These parameters are sampled but not 100% tested.
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W25P240A
TIMING WAVEFORMS
Read Cycle Timing
Pipelined Read Single Read CLK TADSS ADSP TADCS TADCH ADSC TADVS ADV TAS A[15:0] TAH RD2 TWS GW TWS BWE TWH TWH RD3 TADVH Suspend Burst ADSC initiated read TADSH TCYC TKH TKL ADSP is blocked by CE inactive Burst Read Unselected
RD1
BW[8:1] TCES CE TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z TKHZ 1a TOX TKX 2a 2b 2c 2d 3a TKX TOHZ TCEH CE masks ADSP Unselected with CE
DON'T CARE UNDEFINED
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Publication Release Date: February 1998 Revision A4
W25P240A
Timing Waveforms, continued
Write Cycle Timing
Single Write TCYC CLK TKH TKL TADSS ADSP TADCS ADSC TADVS ADV TAS TAH A[15:0]
WR1
Burst Write
Write
Unselected
TADSH
ADSP is blocked by CE inactive
TADCH
ADSC initiated write
TADVH
ADV must be inactive for ADSP write
WR2 WR3
TWS GW TWS BWE TWS BW[8:1] TCES CE TCEH
TWH
GW allows processor address (and BE = BWE) to be pipelined during a writeback
TWH
TWH
WR2 WR3
WR1
CE masks ADSP
Unselected with CE
OE
Data-Out
High-Z TDS TDH BW[8:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a
Data-In
High-Z
1a
DON'T CARE UNDEFINED
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W25P240A
Timing Waveforms, continued
Read/Write Cycle Timing
Single Read CLK TADSS ADSP TADSH
Single Write TCYC TKH TKL
Burst Read
Unselected
ADSP is blocked by CE inactive
TADCS TADCH ADSC TADVS ADV TAS A[15:0]
RD1
ADSC initiated read
TADVH
Suspend Burst
TAH
WR1 RD2
TWS GW TWS BWE
TWH
TWH
TWS TWH BW[8:1] TCES CE TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z 1a TKHZ TDSTDH 1a TOH 2a 2b 2c 2d TKHZ TKX TOHZ TCEH
WR1
CE masks ADSP
Unselected with CE
DON'T CARE UNDEFINED
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Publication Release Date: February 1998 Revision A4
W25P240A
ORDERING INFORMATION
PART NO. SUPPORTABLE BUS SPEED (MHz) 75 66 OPERATING CURRENT MAX. (mA) 350 350 STANDBY CURRENT MAX. (mA) 80 80 PACKAGE
W25P240AF-6 W25P240AF-6A
Notes:
100-pin QFP 100-pin QFP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W25P240A
PACKAGE DIMENSIONS
100-pin QFP
HD D
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
0.01 0.014 0.018 0.113 0.016 0.008 0.555 0.25 2.57 0.20 0.10 13.90 0.35 2.72 0.30 0.15 0.45 2.87 0.40 0.20
E HE
A A1 A2 b c D E e HD HE L L1 y
Notes:
0.101 0.107 0.008 0.012 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.669 0.905 0.025 0.677 0.913 0.031 0.063
14.00 14.10 20.00 20.10 0.802 17.40 23.40 0.95
0.791 19.90 0.032 0.685 0.921 0.037
0.498 0.65 17.00 23.00 0.65 17.20 23.20 0.80 1.60
0.003 0 7 0
0.08 7
e
b
C
A2 See Detail F Seating Plane y A1
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
L L1
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Publication Release Date: February 1998 Revision A4
W25P240A
VERSION HISTORY
VERSION A1 A2 A3 DATE Dec. 1996 Mar. 1997 Aug. 1997 1, 8, 12 8 PAGE Initial Issued Change part no. from W25P240A-75/66 to W25P240A-6/7 A.C. Timing Characteristics: TAS from 2.5 to 1.5 TAH from 0.5 to 1.5 TWS from 2.5 to 2.0 TWH from 0.5 to 1.0 6, 8 A4 Feb. 1998 8, 12 Working temperature range from 70-0 C to 55-0 C Part no. W25P240AX-"7" change to "6A" DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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